In recent years, the pulse width modulation (PWM) Class D digital audio amplifier has been of great interest within the consumer electronics industry due to its superior power efficiency compared to traditional Class A, Class B and Class AB analog amplifiers. Class D amplifiers have been designed with a digital input source and used digital signal processing (“DSP”) to convert the pulse code modulation (“PCM”) audio data into PWM data to drive an appropriate power device. However, the output audio quality of such a digital amplifier has not increased along with the increased efficiency. This is mainly due to the PWM induced distortion and various errors and noise disturbances that occur in different functional blocks of a digital Class D amplifier, i.e., timing errors that happen in the power stage switching devices, quantization noises and power supply disturbances.
Methods and algorithms have been invented to reduce the PWM induced distortion such as described in U.S. Pat. No. 5,617,058 to Adrian, U.S. Pat. No. 6,657,566 to Risbo and U.S. Pat. No. 5,559,467 to Smedley. For a typical power device, disturbances in power supply and timing errors caused by switching characteristics are usually the dominant sources of harmonic distortion at the output. Correction methods and circuits, such as that taught in Smedley, were designed specifically to compensate the power supply errors and variations. In general, previous attempts at correcting total harmonic distortion (“THD”) for digital amplifiers utilized analog feedback from the switching power stage into various topologies.
An analog feedback loop in a digital input amplifier requires either the use of a high-speed feedback circuitry or the use of a high-precision/high-speed A/D converter Both of these choices require sensitive and precise electronics that are difficult to design and are expensive to implement in an integrated circuit (“IC”). With a well-regulated power supply or using other means of correcting for power supply errors, the level of distortion is determined mainly by the timing errors occurring in the power stage. Thus, it becomes possible to digitize the output of the switching power stage, not with a traditional multi-bit A/D converter, but rather a simple comparator circuit that outputs only a two-level, binary signal. This conversion can be performed simply and cheaply in standard complimentary metal-oxide semiconductor (“CMOS”) digital IC processes. Since the power switch is driven directly by a digital signal, it is a simple operation to derive the timing error of the power switch.